(1) Field of the Invention
The invention relates to a method of manufacturing an integrated circuit device, and, more particularly, to a method of performing a chemical mechanical polish in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Chemical mechanical polishing (CMP) is an important processing technology in modern integrated circuit manufacturing. CMP is used to planarize dielectric materials and to remove excess metal layers during the definition of damascene patterns. An additional use of CMP processing is the planarization and height adjustment of polysilicon lines during the formation of anti-fuse memory devices. This application of CMP is of particular importance to the present invention.
Referring now to FIG. 1, a small part of an anti-fuse memory array is shown in cross section. An anti-fuse memory is a non-volatile memory that can be programmed once but not erased. The memory comprises a first array of conductive lines 14 that are formed overlying a substrate 10. Typically, the first array of conductive lines 14 comprises polysilicon that has been doped to either p-type or n-type. In the example case, each line 14 comprises a first polysilicon layer 18, a metal silicide layer 22, and a second polysilicon layer 26 where the second polysilicon layer 26 is lightly doped n-type (N-). A first dielectric layer 30 surrounds the first array of conductive lines 14. A second array of conductive lines 38 and 42 is formed overlying the first array of lines 14. The second array of lines typically comprises a third polysilicon layer 38 that is doped to the opposite type of the second polysilicon layer 26. In this example, the third polysilicon layer 38 is heavily doped p-type (P+). A second metal silicide layer 42 overlies the third polysilicon layer 38.
In the typical arrangement, the first array of conductive lines 14 forms a plurality of bitlines of the memory array. In this case, BITLINE0 and BITLINE1 are shown. A single wordline may cross over several bitlines as is shown by the second conductive line 38 and 42 that is a wordline WORDLINE for the array. It is important to note that a thin layer of dielectric material 34 separates the wordline polysilicon 38 from the bitline polysilicon 26. If this thin dielectric layer 34 where not present, then the wordline polysilicon 38, which is P+, and the bitline polysilicon 26, which is N-, would form a PN junction or diode. The resulting diodes are shown as D0 and D1 in the illustration.
The anti-fuse memory operates as follows. If the thin dielectric layer 34 is intact, then current will not flow from the WORDLINE 38 to BITLINE0 14 or to BITLINE1 14 due to the insulator 34. If, for example, the WORDLINE 38 is biased to a positive voltage, BITLINE0 is grounded, and BITLINE1 is floated, no current should flow from the WORDLINE 38 to BITLINE0 due to the thin dielectric layer 34. The state of this particular bit of BITLINE0 can thereby be determined as “non-programmed” due to the absence of current. However, if the thin dielectric layer 34 between the WORDLINE 38 and this bit of BITLINE0 has become an electrical short circuit, then current will flow from the WORDLINE 38 to the BITLINE0 at this bit location due to the forward bias of the diode D0. The thin dielectric layer 34 becomes a short circuit if a large forward bias voltage from WORDLINE 38 to BITLINE0 is forced. The thin dielectric layer 34 will permanently breakdown and become a short circuit. This represents the “programmed” state of the anti-fuse memory device.
Referring now to FIG. 2, a memory array is shown at a step of formation. The first conductive lines 14′ have been formed by deposition and patterning. At this point, the lines 14′ are substantially taller than the final, desired height 50 after the CMP process is completed. The first dielectric layer 30 has been formed overlying the substrate 10 and the lines 14′ and filling the gaps between the lines. Note the conductive lines 14′ are patterned to a very narrow line-to-line spacing. Therefore, the first dielectric layer 30 must be formed using a technique capable of filling gaps with a high aspect ratio of about three. To achieve this difficult gap fill, a high density plasma (HDP) oxide process is used. In a HDP oxide deposition, the process chemistry and energy levels are set up so that both depositing and etching occur at the same time. That is, the process is both depositing silicon oxide and removing silicon oxide at the same time. The deposition rate is higher than the removal rate so that a net deposition occurs. This process is capable of filling very narrow, high aspect ratio, topologies. The HDP oxide process also results in a very distinctive saw tooth pattern 46 overlying each of the conductive lines 14′.
Referring now to FIG. 3, a CMP process is then performed to remove excess first dielectric layer 30 and to polish down the conductive lines 14 to the final, desired height. This polishing down operation is typically performed using a timed CMP process. Several problems are experienced at this process step. First, the CMP process exhibits poor uniformity both across the wafer and from wafer to wafer. The cross section shows the result in an exaggerated form where the thickness T1 of the N- polysilicon layer 26 BITLINE0 is substantially greater than the thickness T2 of the N- polysilicon layer 26 of BITLINE1. It is found that the final thickness of the N- polysilicon must be carefully controlled to achieve a small leakage current in the final anti-fuse devices. Unfortunately, the within wafer variation of thicknesses T1 and T2 for the N- polysilicon layer 26 can be between about 600 Å and about 1,000 Å using the timed CMP process.
In addition, the post-CMP thickness is monitored using a polysilicon monitor pad. It is found that the correlation between the polysilicon monitor pad measurement and the actual device N- polysilicon thickness is poor. Further, the correlation becomes worse as array density is increased. The offset between the post-CMP thickness of the monitor pad and of the devices is very difficult to control in the production process. As a result of these observations, an improved method of polishing down the polysilicon bitlines of the anti-fuse memory device is very desirable.
Several prior art inventions relate to chemical mechanical polishing (CMP) methods. U.S. Pat. No. 5,670,410 to Pan teaches a method to form an analog capacitor with a topmost electrode comprising polysilicon. The electrode acts as a marker to detect the endpoint of a CMP operation on an overlying dielectric layer. U.S. Pat. No. 6,391,768 B1 to Lee et al describes a method to chemical mechanical polish a metal layer overlying a dielectric layer. An anti-reflective coating (ARC) is used as a stop layer. One embodiment comprises a silicon oxynitride ARC layer over a silicon oxide layer. Another embodiment comprises a TEOS oxide layer overlying a high-density plasma oxide layer. U.S. Pat. No. 6,261,851 B1 to Li et al describes a method and an apparatus to detect and to monitor ammonia gas given off as a bi-product in a CMP operation. The invention may be used to detect a transition from an oxide layer to a silicon nitride etch stop layer during the polishing step. U.S. Pat. No. 6,294,457 B1 to Liu describes a method to prevent particle contamination during an argon (Ar) sputter operation used for pre-cleaning metal. An oxide layer is optimally placed as the topmost, exposed layer during an Ar sputter pre-clean of a tungsten (W) metal plug. Any bi-products from the sputtering of the oxide will adhere to the quartz walls of the process chamber and not precipitate as contamination particles.